1. Field
The disclosed technology relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a MOSFET using a blanket layer with large stress.
2. Description of the Related Technology
When a feature size of a semiconductor device is being scaled down from the 90 nm CMOS integrated circuit process, stress channel engineering plays a more and more important role for increasing carrier mobility in a channel. Various processes for inducing uniaxial stress, i.e. compressive stress or tensile stress in a channel direction, are applied to the method for manufacturing a semiconductor device to increase carrier mobility and improve performances of the semiconductor device. For example, in the 90 nm CMOS process, the compressive stress is introduced in a PMOS device by embedded SiGe (e-SiGe) source/drain regions, or by a 100 substrate with a tensile contact etch stop layer (tCESL). In the 65 nm CMOS process, a first-generation source/drain stress memorization technique (SMT×1) is used on the basis of the 90 nm CMOS process, in which double etching stop layers are used. In the 45 nm CMOS process, a second-generation source/drain stress memorization technique (SMT×2) is used on the basis of the previous generation of the CMOS process, in which an e-SiGe technique is used in combination with a single tCESL or double tCESLs, and a stress proximity technique (SPT) is also used. Moreover, a 110 substrate is used for a PMOS device and a 100 substrate is used for an NMOS device. Beyond the 32 nm CMOS process, a third-generation source/drain stress memorization technique (SMT×3) is used on the basis of the previous generation of the CMOS process, in which tensile stress in the NMOS device is enhanced by embedded SiC source/drain regions.
Moreover, the techniques of introducing stress into the channel region may be implemented by controlling materials and profiles of a channel region or a sidewall spacer, instead of varying materials of the substrate and/or source/drain regions. As an example, a double stress liner (DSL) technique may be used, in which a sidewall spacer of SiNx is used for introducing tensile stress in an NMOS device and a compress-stress sidewall spacer is used for introducing compressive stress in a PMOS device. As another example, the embedded SiGe source/drain regions may be formed as having a cross section of Σ shape to improve the stress in a channel region of a PMOS device.
However, effects of these conventional stress techniques may be impaired when a feature size of a semiconductor device is further scaled down. For an NMOS device, misalignment and deviation of various films, which introduce stress, will be more serious when the features size of the semiconductor device is further scaled down. In turn, it requires that the films have small thicknesses while introducing large stress. For a PMOS device, carrier mobility in a channel region remarkably depends on a feature size of a semiconductor device in the technique using embedded SiGe source/drain regions. Scaling down of the feature size impairs the effect of increasing carrier mobility.
A novel idea is to use a diamond-like amorphous carbon (DLC) film to increase intrinsic stress of the device. For example, an article entitled “A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET” by Kian-Ming Tan etc., IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008, discloses that DLC, which has compressive stress larger than SiN, covers the whole surface of a MOSFET. The larger compressive stress of the DLC may be transferred to an underlying channel region to increase carrier mobility of a channel region and improve performances of the semiconductor device. Moreover, a US patent application No. US2010/0213554A1 discloses a similar structure.
Conventionally, the DLC is formed by magnetically filtered cathodic vacuum arc (FCVA). The DLC is more like diamond than graphite by increasing a ratio of SP3 bond, and in turn has increased intrinsic stress. However, the FCVA process for forming the DLC with large stress is not a standard process used in integrated circuits. For example, it is incompatible with a conventional CMOS process. Additional manufacture apparatus, processes and time may be needed. Moreover, the FCVA process generates many particles which adversely affect the following processes. The particles remaining in a fine structure cause undesired electrical conduction or insulation, or uneven thickness of the film to be formed, or variations of the device due to thermal stress, and so on. Consequently, reliability of the device may be poor. Alternatively, the inventor proposes in a previous patent application that high-quality DLC may be deposited by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, or the like and magnitude of stress of the DLC may be adjusted by controlling the process parameters.
However, no matter what kind of process the DLC is formed with, there are many difficulties in using the DLC as a stress liner, because the DLC is a diamond-like amorphous carbon film in its nature, and has high hardness and poor step coverage. One difficulty is foreseeable that a DLC stress layer may have a small thickness (for example, about 10-50 nm) due to an overall size of the semiconductor device, if the DLC stress layer covers a gate, a sidewall spacer and source/drain regions. The DLC stress layer may have a smaller thickness or even does not remain near a lower portion of the sidewall spacer where the sidewall spacer adjoins the source/drain regions, because the DLC stress layer has poor step coverage. The portion of the DLC stress layer is close to a channel region of the device, but may have a thickness insufficient for applying large stress to the channel region. Consequently, carrier mobility may not be increased as required, which results in unfavorable performances of the device. Moreover, when DLC is used in a sidewall spacer instead of SiN, the sidewall spacer may crack or flake at a sidewall of a gate due to improper process control, in a case that the sidewall spacer should have a small thickness. Consequently, the sidewall spacer may achieve no effect of applying stress to the channel region.
Thus, the previous techniques of introducing high stress by DLC have the drawback of poor step coverage, and are difficult to effectively increase carrier mobility in the channel region and effectively improve driving capability of the device.